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Accelerating Cryptography with Open-Source SoCs
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Lecturer: Patrick Schaumont
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Abstract: In this tutorial, the audience will get a hands-on introduction to the common mechanisms for cryptographic acceleration using custom hardware in the context of System-on-Chip design, including memory-mapped coprocessors and custom-instruction extensions.
The objective of this tutorial is to introduce all the steps included in the development of an embedded SoC application configured around the IBEX (RISC-V) processor:
- Firmware development on an IBEX (RISC-V) open-source processor and functional verification using cycle-accurate simulation.
- Design, functional verification, and performance evaluation of memory-mapped accelerators for cryptography.
- Design, functional verification, and performance evaluation of instruction-set extensions for cryptography.
- Evaluation of the hardware design cost and performance of accelerators based on the OpenROAD ASIC design flow and open-source PDK.
Attendees should have a working knowledge of hardware design including register-transfer level hardware description and synchronous logic design. The ideal candidate would have taken an undergraduate-level course in logic design as well as in embedded software (firmware and bare-metal) programming.
Attendees do not need to have previous experience with ASIC design. Most of the design code will be provided, and the assignments will be of the form ’Analyze what happens if you change X to Y and run the tools again’.